This application claims the priority benefit of Taiwan application serial no. 92114350, filed on May 28, 2003.
1. Field of the Invention
This invention generally relates to a stack-gate flash memory array, and more particularly to a stack-gate flash memory array to prevent leakage due to erratic bits.
2. Description of Related Art
Nonvolatile memory is memory storage technology that does not lose stored information when the power supply is turned off. Some examples of nonvolatile memory are ROM (Read Only Memory), PROM (Programmable Read Only Memory), EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), Mask ROM, and flash memory. Memory chips, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), are considered volatile memory, in that once the power supply is cut off, the stored data is lost.
However, technological advances have resulted in non-volatile memory chips such as EPROM, EEPROM. Flash memory is a type of EEPROM that can be manipulated in blocks, rather than in single bytes. Unlike, EPROM, it does not require UV light to erase the memory. It also does not require any special voltages to be erased and reprogrammed within a system. The design of the flash memory microchip is based on floating gate technology, where a charge is transferred through an oxide layer into a conductive floating gate and stored. This technology allows a section of memory cells to be erased in a single action. Through Fowler-Nordheim tunneling electrons penetrate a thin layer of dielectric material to remove an electronic charge from the floating gate, which is associated with each memory cell. Hence, flash memory equips with both nonvolatility and ability of random access, and thus is widely used.
FIG. 1 is a circuit diagram of a conventional stack-gate flash memory array. This memory array includes 2N*2M memory cells (transistors) connected by a group of bit lines BL0-BL2Mxe2x88x921, a group of word lines WL0-WL2Nxe2x88x921, and a common source line SL. When a flash memory cell, e.g., memory cell 102 (the transistor at the intersection of BL1 and WL1) is over erased and thus represents an erratic bit, the transistor will be turned on even without working voltage applied to the control gate and thus generates a leakage current. This leakage current affects other memory cells such as memory cells 104 and 106, that are connected to the same bit line BL1 and causes data inaccuracy stored in those cells.
To avoid data inaccuracy, the affected cells have to be erased and then reprogrammed. However, because of using the common source line SL in the conventional stack-gate flash memory array, all cells must be erased at the same time. Hence, it takes longer to do so.
Flash memory also limits how often you can erase and rewrite the same area. This number, (known as the cycling limit) depends on the specific flash memory technology, but it ranges from a hundred thousand to a million times per block. As a region of flash memory approaches its cycling limit, it begins to suffer from sporadic erase failures. With further use, these erase failures become more and more frequent. Eventually, the medium is no longer erasable and thus no longer writable, although the data already resident is still readable. Hence, the manufacturers will use firmware to count how many times a block is rewritten. When the count reaches to a predetermined number, this particular block will never be used and the size of the flash memory becomes smaller. Hence, a solution to reduce the frequency of the erasing/rewriting operation due to the leakage current is needed to extend the flash memory""s lifetime.
An object of the present invention is to provide a stack-gate flash memory array to avoid the effect of the leakage current resulting from the erratic bits.
Another object of the present invention is to provide a stack-gate flash memory array to reduce the frequency of the erasing/rewriting operation and to extend the flash memory""s lifetime.
The present invention provides a stack-gate flash memory array. In the present invention, one bit line for a conventional memory cell had been divided two independent bit lines; two word lines have been combined together via the gate terminal of an isolated transistor. Because the bit lines are divided and the word lines will stop the leakage current via the isolated transistor, the leakage current would not affect the other memory cells. Hence, the present invention can avoid the data inaccuracy due to the leakage current resulting from the erratic bits, and thus can extend the flash memory""s lifetime.
The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.